Project R2 - Architecting the Next Evolution of Secure Silicon
In the world of hardware, the letter 'R' has many meanings: RISC, Robust, Resilient, Revolutionary . Architecture, R2 , embraces all of them. Built on the foundation of RISC-V, R2 is a clean-slate design that moves security from the software layer, primarily into the physical wiring of the CPU. R2 doesn't just ask the software to be "good"—it makes hardware physically incapable of being "bad." Here is how we are redesigning the core to kill the most common attack vectors at the silicon level. 1. R2-Tags: Data Isolation at 0-Cycles In a standard CPU, data is just bits. To an R2 processor, every 64-bit word is accompanied by a Metadata Security Tag . If "Trusted" data interacts with "Untrusted" data, the hardware automatically taints the result. The execution stage physically disconnects the "Write" signal if a tainted pointer tries to access a secure memory region. 2. The R2-Buffer: Zer...